max 数字频率计 顶层文件VHDL仿真编译时出现如下图问题，跪求高手帮帮我

译码器 entity decoder3_8 is port(a:in std_logic_vector(2 downto 0); qc:out std_logic_vector(3 downto 0)); end decoder3_8; architecture rtl of decoder3_8 is begin process(a) ... 译码器
entity decoder3_8 is
port(a:in std_logic_vector(2 downto 0);
qc:out std_logic_vector(3 downto 0));
end decoder3_8;

architecture rtl of decoder3_8 is
begin
process(a)
begin
case a is
when"000"=>qc<="0000";
when"001"=>qc<="0001";
when"010"=>qc<="0010";
when"011"=>qc<="0011";
when others =>qc<="1111";
end case;
end process;
end rtl;

模块 CH

entity ch is
port(sel:in std_logic_vector(2 downto 0);
a3，a2，a1，a0，dang:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end ch;

architecture ch_arc of ch is
begin
process(sel)
begin
case sel is
when"000"=>q<=a0;
when"001"=>q<=a1;
when"010"=>q<=a2;
when"011"=>q<=a3;
when"111"=>q<=dang;
when others=>q<="1111";
end case;
end process;
end ch_arc;

选择模块
entity sel is
port(clk:in std_logic;
sl:out std_logic_vector(2 downto 0));
end sel;
architecture sel_arc of sel is
begin
process(clk)
variable cnt:std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then
cnt:=cnt+1;
end if;
sl<=cnt;
end process;
end sel_arc;

顶层文件：
ENTITY hql IS
PORT(clr，sig，clk:IN STD_LOGIC;
alm:OUT STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
qc :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
END hql;
ARCHITECTURE sd OF hql IS
COMPONENT fen
port(clk:in std_logic;
q:out std_logic);
end COMPONENT;
COMPONENT selx
port(clk:in std_logic;
sl:out std_logic_vector(2 downto 0));
end COMPONENT;
COMPONENT corna
port(clr，sig，door:in std_logic;
alm:out std_logic;
q3，q2，q1，q0，dang:out std_logic_vector(3 downto 0));
end COMPONENT;
COMPONENT lock
port(l:in std_logic;
a4，a3，a2，a1，a0:in std_logic_vector(3 downto 0);
q4，q3，q2，q1，q0:out std_logic_vector(3 downto 0));
end COMPONENT;
COMPONENT ch
port(sel:in std_logic_vector(2 downto 0);
a3，a2，a1，a0，dang:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end COMPONENT;
COMPONENT disp
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end COMPONENT;
COMPONENT decoder3_8
port(a:in std_logic_vector(2 downto 0);
qc:out std_logic_vector(3 downto 0));
end COMPONENT;

SIGNAL qq:STD_LOGIC;
SIGNAL qq3，qq2，qq1，qq0，qqdang:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tt4，tt3，tt2，tt1，tt0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ww:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SS:STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN
u1:fen PORT MAP(clk=>clk，q=>qq);
u2:selx PORT MAP(clk=>clk，SL=>SS);
u3:corna PORT MAP(clr=>clr，sig=>sig，door=>qq，alm=>alm，q3=>qq3，q2=>qq2，q1=>qq1，q0=>qq0，dang=>qqdang);
u4:lock PORT MAP(l=>qq，a4=>qq3，a3=>qq3，a2=>qq2，a1=>qq1，a0=>qqdang，q4=>tt4，q3=>tt3，q2=>tt2，q1=>tt1，q0=>tt0);
u5:ch PORT MAP(sel=>SS，a3=>tt4，a2=>tt3，a1=>tt2，a0=>tt1，dang=>tt0，q=>ww);
u6:disp PORT MAP(d=>ww，q=>q);
u7:decoder3_8 PORT MAP(a=>SS，qc=>qc);
END sd;
由于超出字数所以把库说明头程序删了